This invention relates to a decoding circuit, a code conversion circuit and to a code converting method.
As a conventional code conversion circuit for converting an input digital code of a preset bit length (width) into another digital code, a decoding circuit is now explained. The decoding circuit receives an input signal, which gives e.g., six different values (0, 1, 2, 3, 4 and 5), and is represented by three bits in binary representation. The decoding circuit determines a set of two adjacent bits, each being at the logic value 1, depending on the input signal in six bits of an output signal representing a decoded result signal.
The decoding circuit is used in, for example, a circuit and the like adapted to supply a selection signal to a selector which receives e.g., six signals (signals to be selected) and which outputs at least two of the signals neighboring to each other. Referring to FIG. 6, which is used in the explanation of the present invention, the outline of the conventional decoding circuit is explained. This decoding circuit 80, shown in FIG. 6, has a clock selector 70 which generates signals (S0, S1, S2, S3, S4 and S5) for selecting sets of, for example, (CK0, CK1), (CK1, CK2), (CK2, CK3), (CK3, CK4), (CK4, CK5) and (CK5, CK0) from six-phase clocks (CK0, CK1, CK2, CK3, CK4, CK5) in a clock selector 70, depending on count value of (0-5) of a binary counter 110, and output the so selected sets.
If a signal to be selected corresponding to the selection signal which has a value of logic 1 is selected, and a signal to be selected corresponding to the selection signal which has a value of logic 0 is not selected, a rule for generating 6-bit selection signals (S0, S1, S2, S3, S4, S5) from 3-bit input signals is given as follows:
input signalsxe2x86x92(S0, S1, S2, S3, S4, S5)
000xe2x86x92110000,
001xe2x86x92011000,
010xe2x86x92001100,
011xe2x86x92000110,
100xe2x86x92000011,
101xe2x86x92100001.
where it is noted that the input signals are derived from an output (count value) of the binary counter (110 of FIG. 6).
Meanwhile, as is well known, the decoding circuit (combinatorial circuit) receiving a N-bit signal for outputting 2N-bit decoded result signal is increased in circuit scale with an increasing value of N.
Accordingly, it is an object of the present invention to provide a decoding circuit, a code conversion circuit and a code conversion method, whereby it is possible to decrease the circuit scale.
In accordance with one aspect of the present invention, the above and other objects are satisfied at least in part by providing a decoding circuit which receives as an input a 2N-bit signal composed of a N-bit signal and a signal obtained on inverting respective N-bits of said N-bit signal, where N is an integer not less than 2, and which is adapted to generate 2N types of decoded signals on inverting one bit in said 2N-bit signal received, wherein on the premise that the 2N-th bit and the first bit composing respectively one and other ends of the 2N-bit signal are adjacent to each other, among the 2N-bits of said decoded signal, one bit (if N=2), or neighboring plural (Nxe2x88x921) bits (if N less than 2), is/are of a first value, with the remaining bits being of a second value.
In the decoding circuit in accordance with the present invention, in which the 2N-th bit and the first bit at both ends of said 2N-bit signal composed of the N-bit signal and the signal obtained on inverting respective bits of said N-bit signal, are adjacent to each other, mutually neighboring N bits are preferably of a first value in succession.
In the decoding circuit in accordance with the present invention, said N-bit signal and the signal obtained on inverting respective bits of said N-bit signal are obtained preferably from non-inverting output terminals and inverting output terminals of N stage flip/flops composing a ring counter.
In the circuit in accordance with the present invention, said ring counter comprises: said N stage flip/flops; and N pieces of logic circuits, each of which is arranged for each of said flip/flops of said N stage flip/flops and each of which is adapted for supplying an input signal for the associated flip/flop, wherein each of said logic circuits, receiving as inputs an up signal, a down signal and a hold signal, indicating up-count, down-count and hold operations, respectively, is adapted so that in case of up-count operation of said ring counter, an inverted signal of an output of the last-stage flip/flop is fed back and input to said first stage flip/flop through the logic circuit associated with the first stage flip/flop, during shift operation by clock, the output state of a preceding stage flip/flop being through each of said logic circuits, propagated to an input of a succeeding stage flip/flop; in case of down-count operation of said ring counter, an inverted signal of an output of the initial stage flip/flop is fed back and input to said last stage flip/flop through the logic circuit associated with the last state flip/flop, during shift operation by clock, the output state of a succeeding stage flip/flop being through each of said logic circuits, propagated to an input of a preceding stage flip/flop; and in case of hold operation of said ring counter, an output signal of each flip/flop associated with each of said logic circuits is fed to an input of the flip/flop associated with each said logic circuit.
In the circuit in accordance with the present invention, there is provided a coincidence detection circuit for detecting the coincidence between said up signal and the down signal: an output of which is applied to each of said logic circuits as said hold signal.
In the circuit in accordance with the present invention, there is provided a circuit for coping with an exceptional pattern, occurrence of which is not assumed, said circuit including: means for receiving to output signals of said N-stage flip/flops composing said ring counter to detect said exceptional pattern; and means for substituting a pattern, occurrence of which is allowed, for said exceptional pattern on detection of said exceptional pattern to provide the pattern, occurrence of which is allowed, as an input to said decoding circuit.
A code conversion method in accordance with another aspect of the present invention includes the following steps,
step 1: generating, by code generating means, a 2N-bit signal, composed by a N-bit signal and a signal obtained on inverting the respective N-bits of said N-bit signal, where N is an integer not less than 2; and
step 2: generating by code conversion means, 2N types of signals from said 2N-bit signal generated by the step 1, on inverting one bit of said 2N-bit signal, wherein with the 2N-th bit and the first bit at either ends of the 2N-bit signal being adjacent to each other,
among the 2N-bits,
one bit is, if N=2, or
plural neighboring (Nxe2x88x921) bits are, if N greater than 2,
of a first value, with the remaining bits being of a second value.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein only the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.